Field
Aspects of the present innovations relate generally to multi-bank memory circuitry, and, more specifically, to systems and methods involving capturing and propagating addresses and write data through multi-bank memory circuitry.
Description of Related Information
In Quad-B2 SRAMs, by way of example, the two operations of a read and a write may be initiated per clock cycle, and two beats of data are transferred per operation per clock cycle (i.e. data transfers are DDR—double data rate).
As depicted in FIG. 1, a read operation is initiated by synchronously asserting the R#32 control pin “low” at the rising edge of the K 62 input clock 101, and by synchronously providing the read address (Read1, Read2, Read3 in each cycle #1, #2, and #3, respectively) on the A address pins at the rising of the K 62 input clock 103.
A write operation is initiated by synchronously asserting the W#34 control pin “low” at the rising edge of the K 62 input clock 102, by synchronously providing the write address (Write1, Write2, Write3 in each cycle #1, #2, and #3, respectively) on the A 42 address pins at the rising of the K#64 input clock a half cycle later 104, by synchronously providing the first beat of write data on the D 52 data pins at the rising edge of the KD 54 input clock (D10/D20/D30 in each cycle #1, #2, and #3, respectively) 105, and by synchronously providing the second beat of write data on the D 52 data pins at the rising edge of the KD#56 input clock a half cycle later (D11/D21/D31 in each cycle #1, #2, and #3, respectively) 106.
Note that the K#64 input clock is the inverse of the K 62 input clock, and the KD#56 input clock is the inverse of the KD#56 input clock. K 62 and K#64 are nominally 180 degrees out of phase, as are KD 54 and KD#56, but both pairs of clocks are allowed to have some amount of phase offset away from 180 degrees. KD/KD#54/56 can either be mesochronous with, or physically the same as, K/K#62/64. When KD/KD#54/56 are mesochronous with K/K#62/64, they are the same frequency and are generated from the same source clock, but are allowed to have some amount of phase offset.